IBM STRENGTHENS POWER ARCHITECTURE WITH NEW LOW-POWER PROCESSORS
EAST FISHKILL, N.Y., October 4, 2006 - IBM (NYSE: IBM) today announced new, low-power additions to its Power Architecture line of microprocessors and new processor cores that address the growing demand for high-performance processors that conserve energy.
In addition, the company expanded a university program designed to encourage development of broadband applications based on Power Architecture, which now accounts for a significant amount of all chip technology found in today's automobiles, supercomputers, network and communications equipment, printers and gaming consoles.
"Innovation in microprocessors is no longer about simply raising the bar on speed," said Ron Martino, director, Power Architecture Solutions, IBM Technology Collaboration Solutions. "IBM is committed to the development of high-performance, energy-efficient processors for a wide range of enterprise and consumer applications."
Specifically, IBM introduced two new off-the-shelf standard PowerPC single-core processors, both available immediately. The PowerPC 750CL, a 32-bit microprocessor, consumes half the energy as its predecessor, and performs at speeds ranging from 400MHz to 1GHz. The 750CL includes a 256KB L2 cache, and is targeted at networking, storage, imaging, consumer electronic and other high-performance embedded applications.
The PowerPC 970GX, a follow-on to the PowerPC 970FX, supports both 32-bit and 64-bit operations. It features the same power capabilities as its predecessor, but incorporates twice the integrated L2 cache at 1MB. The range of frequencies for the 970GX is 1.2 to 2.5GHz, enabling the chip to support high-bandwidth data processing and algorithmic intensive computations, making it suitable for communications, storage, multimedia and graphics based devices.
IBM also introduced the CPC965, a companion chip to the 970 series of processors designed to provide I/O connectivity and run at significantly less power than comparative bridge chips. The highly integrated CPC965 features a very high speed front bus that operates at up to half the processor frequency. Shipment of CPC965 samples is planned for March 2007.
IBM also announced three new 32-bit processor cores, including:
Advances found within all three processor cores include:
Both PowerPC processors and the two ASIC hard cores are manufactured using IBM’s 90 nanometer (nm) copper processing technology. The microprocessors also feature silicon-on-insulator (SOI) technology.
The 464 H90 hard core preliminary design kit is targeted for availability at the end of the year with the 464FP H90 preliminary design kit targeted in first quarter 2007. The planned availability of the 460S is second quarter 2007.
Last December, IBM announced plans to make the specifications of the PowerPC 405 core available at no cost to the academic and research community. The program was initiated in April to respond to requests by leading educators in computer science and participants in collaborative multi-core processing research projects who were looking to advance next-generation networking and communications devices, such as gaming consoles, mobile devise and consumer electronics.
Since then, 14 universities worldwide have joined the program and are leveraging the PowerPC 405 core. They are: Peking University, Saarland University, University of Maine, Shanghai Research Center for IC Design, University of Karlsuhe, Duke University, Harbin Institute of Technology, Stanford University, Yildiz Technical University, Helsinki University of Technology, Rice University, University of Illinois at Urbana-Champaign, Xi'an Jiaotong University and the University of Massachusetts at Amherst. In addition, Stanford University has signed the RAMP (Research Accelerator for Multiple Processors) license, giving them limited architecture rights for research purposes.
In other university-related news, Morgan State University recently received a grant from IBM to conduct teaching and research around Power Architecture technology. This semester, Power Architecture is being taught in three undergraduate courses in the department of electrical and computer engineering at Morgan State, located in Baltimore and designated as Maryland's public urban university.
As development time and system-on-chip (SOC) complexity increase, the need to perform early design evaluation, parallel software development, simulation and co-verification increases. IBM recently signed agreements with leading EDA tool vendors Synopsys Inc., Mentor Graphics Corp., Summit Design Inc., CoWare Inc. and Poseidon Design Systems. CoWare will also be developing a processor support package for IBM's new PowerPC 750CL processor.
IBM is a founder member of Power.org, a community
of more than 40 companies driving innovation around Power Architecture
Power.org provides an open ecosystem through which its members
engage in collaborative innovation on Power Architecture technology.
Power.org’s mission is to optimize interoperability, accelerate
innovation and drive increased adoption of this leading processor
architecture. For more details, visit http://www.power.org
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Source : IBM